FIG. 1 schematically shows a circuit of an SRAM cell. The memory cell comprises two cross-coupled inverters Inv0 and Inv1 in antiparallel, output terminal Out0 of inverter Inv0 being connected to input terminal In1 of inverter Inv1, and output terminal Out1 of inverter In1 being connected to input terminal In0 of inverter Inv0. Inverter Inv0 comprises a P-channel MOS transistor (PMOS) 1 and an N-channel MOS transistor (NMOS) 3 series-connected between a power supply potential Vdd connected to the source of PMOS transistor 1, and a ground potential Gnd connected to the source of NMOS transistor 3. The drains of transistors 1 and 3 are coupled together to output terminal Out0 of inverter Inv0, the gates of transistors 1 and 3 being coupled together to input terminal In0 of inverter Inv0. Inverter Inv1 comprises a PMOS transistor 5 and an NMOS transistor 7 series-connected between potential Vdd connected to the source of PMOS transistor 5, and ground potential Gnd connected to the source of NMOS transistor 7. The drains of transistors 5 and 7 are coupled together to output terminal Out1 of inverter Inv1, the gates of transistors 5 and 7 being coupled together to input terminal In1 of inverter Inv1.
Terminals In0 and Out1 are connected to a bit line 9 via an NMOS transfer transistor 11 and terminals Out0 and In1 are connected to a bit line 13 via an NMOS transfer transistor 15. Thus, a value stored by the memory cell may be written into or read from via bit lines 9 and 13 by applying a control potential Ctrl to the gates of transfer transistors 11 and 15.
In this memory cell, the PMOS transistors of the inverters inv1 and inv0 are all identical and have a same threshold voltage VtP, and the NMOS transistors of the inverters inv1 and inv0 are all identical and have a same threshold voltage VtN.
The electric dynamic power consumption of a circuit comprising an SRAM memory whose memory cells are of the type described in relation with FIG. 1 particularly depends on the square of the power supply voltage of this circuit which is generally limited by the power supply or operating voltage Vdd of its SRAM memory. It would be desirable to provide an SRAM cell having an operating voltage Vdd as low as possible to decrease the power consumption of a circuit comprising an SRAM memory.